In asynchronous digital logic circuits, signals propagate throughout the circuit to create the desired results. In designing these circuits careful attention must be paid to gate delays to ensure proper device operation. To maximize operating speed these delays must be minimized.
One problem which may occur in digital circuits is a noise "glitch" wherein a logic level incorrectly changes polarity for a short amount of time. This erroneous transition may propagate throughout the circuit. For example, in a memory array if the address is latched during a noise glitch, the wrong address will result which may lead to an unrecoverable system error.
In prior art methods, glitch filters have been developed which will eliminate the possibility of glitches of a certain time length. The problem with these filters is the relatively long delay compared with the duration of the glitch to be filtered. The delays caused by the glitch filters undesirably slow the circuit.
Accordingly, improvements which overcome any or all of the problems are presently desirable.